Turning to FIG. 1, illustrated is a prior art multiplying delay locked loop (MDLL) 100. In the DLL 100, a reference clock line 101 and a feedback line 103 are coupled into a first and second input of a multiplexer (MUX) 110, respectively. An output signal of the MUX 110 is selected by a selector line 105. An output line of the MUX 110 is coupled into a delay circuit 120, having series-coupled phase delay elements 122, 124, and 126.
An output of the delay circuit 120 is DLLOUT 160. DLLOUT 160 is coupled into a divider circuit (divide-by-M) 150. An output of the divider circuit 150 is coupled into a first input of a phase detector/charge pump 130. The reference clock line 101 is also coupled into a second input of the phase detector/charge pump 130. An output of the phase detector/charge pump 130 is coupled to an cathode of a capacitor 140, an anode of which is coupled to ground. The cathode of the capacitor 140 is coupled to a signal input of the delay elements 160. A delay of the delay circuit 160 is proportional to a voltage measured across the capacitor 140.
Generally, the MDLL 100 can be used to multiply a frequency of a reference source (i.e., a clock signal on reference clock line 101) through employment of the divider circuit 150.
A primary advantage of MDLL over a “phase locked loop” (PLL) circuit is that a noise that is associated with a “voltage controlled oscillator” is not integrated within the MDLL 100, and therefore a lower “root mean square” (RMS) jitter occurs.
However, a disadvantage of the MDLL 100 is that a “static phase offset” jitter is typically higher than a PLL. A “static phase offset” can be generally defined an average difference in time between the phases of an input clock signal, such as input clock signal on reference clock line 101, and the corresponding phase of the DLLOUT 160. This static phase offset jitter can then result in undesired harmonics, i.e. a spur, at the output of the MDLL 100.
Various approaches towards reducing the “static phase offset” jitter has been taken in the prior art. One approach is that of a MDLL 200, such as described in “A DLL-Based Programmable Clock Multiplier in 01.8 um CMOS with −70 dBc Reference Spur” P. C. Maulik, et al. IEEE JSSC, Vol. 42, No. I, August 2007.
In the prior art MDLL 200, a sample and hold phase detector 260, employs sampling to help reduce the “static phase offset between the REF and FB paths.
Also, the MDLL 200 employs an auto-zeroed trans conductance amplifier 270 instead of a charge pump.
Also, a loop filter 280 is coupled to an output of the an auto-zeroed trans conductance amplifier 270 instead of a charge pump. The sample and hold phase detector 260 is employed to measure very small phase errors between the reference and feedback clocks. The auto-zeroing transconductance amplifier 270 is employed to further reduce static phase offsets introduced due to input offsets in a simple single-ended amplifier. However, a main disadvantage with the above technique is the additional complexity and power dissipation due to the sample and hold and the auto-zero transconductance amplifier circuits.
Turning to FIG. 3, illustrated is an alternative prior art MDLL 300 that attempts to address the problem of spur noise. This MDLL 300, as discussed in U.S. Publication No. 2011/0109356 A1 to Ali, et al. “Aperture Generating Circuit for a Multiplying Delay-Locked Loop”. The MDLL 300 adjusts a select signal aperture to reduce a reference spur jitter using phase interpolators. The main disadvantage with this approach is the complexity and power dissipation associated with generating multiple phases using the interpolators and the additional logic to choose the correct phase.
Therefore, there is a need in the art to address at least some of the issues associated with the previous approaches.